Over the past 40-or-so years there has been a large trend in digitalisation of electronics, from complex systems to relatively simpler sensing and measurement nodes.  Grid connect technology has largely been unimpacted over this period, until relatively recently as the demand for more power from AI Data Centres in particular, plus the adoption of more Green Energy production (PV and Wind) for direct-to-grid connection has put demands on the connection technology; essentially a low frequency transformer. 

The Solid State Transformer (SST) is a new way to connect to the Medium Voltage transmission network, enabling both up-link (energy to the grid) and down-link (energy from the grid) to be implemented in both a reduced physical size and more controllable and reactive (to load demand) system. 

This primer presentation is a look at the methods and some of the technologies used in implementing of what is essentially a digital transformer for modern power connection.  Recent SST interest has been spurred-on by the convergence of new energy production, Electric Vehicle charging and Battery Energy Storage Systems and AI Data Centre demands which has brought together technologies from these separate systems into a cohesive new option for the Low Voltage side power distribution.  The primer also looks at how these new energy systems link together with the SST to provide a new power paradigm for distributed energy supply.

The talk will cover practical guidance on patents and registered designs for hardware and electronics, from PCB layouts and custom silicon/IC designs through to embedded algorithms and physical enclosures. This includes advice on the value of a patent or design for the latest technologies, including how to broadly protect a specific circuit or chip architecture, and trade-offs between trade secrets and patents for advanced fabrication processes. A discussion on the possibility of protecting software, including AI and other algorithms, will touch on common misconceptions and tips for what may be patentable. High levels of package integration, particularly with xPUs and stacked memory dies in a 3D package offer a plethora of opportunities for protecting various hardware, interconnect, chip architecture and package configurations as well as the methods of operating such advanced devices, and the talk will provide some guidance on how even small changes to a semiconductor package may yield patentable subject matter. The role of registered designs, which may offer complimentary protection to patents will be discussed particularly in the context of protecting the appearance of visually aesthetic hardware and software.

Moving a semiconductor technology from a successful laboratory demonstration to a reliable, scalable commercial product is not a straightforward process. As technologies move beyond R&D, engineering challenges increasingly emerge at the interfaces between fabrication, packaging, thermal management, electronics, testing and qualification. Processes that work at prototype level must become repeatable and manufacturable, while performance, yield, reliability, cost and supply-chain constraints begin to shape engineering decisions. At the same time, successful commercialisation requires more than proving that the technology works: product design, customer and market requirements, business strategy, cost, regulatory and international trade requirements, and building the right team - all need to be considered early to ensure there is a realistic pathway from technology to a commercially viable product.

Based on real-world examples and insights from Scotland’s Critical Technologies Supercluster and the Product Design Scotland network, this presentation will explore both the technical and commercial challenges encountered on the journey from semiconductor R&D to market-ready hardware products.  The presentation will also highlight how closer collaboration between technology developers, product designers, manufacturers, integration specialists and wider ecosystem can reduce risk, avoid costly redesign and create more effective pathways from promising technology to sustainable operations.

Emerging 800 V DC architectures for AI data centres are driving new power system and device requirements. The data centre power distribution is working on removing power conversion stages and supplying high voltage closer to the racks. To meet this, the high-voltage PSU is being required to shrink, and become more efficient, while also converting 800 V down to 50, 12, or even six, all while maintaining safety isolation. This in turn demands the power device switching at higher frequencies while improving the figure of merit (gate charge, output charge, etc).

This is where GaN shines as the correct power device for the future. With much lower gate drive requirements than SiC or silicon, gate driving losses are reduced. With compact, low-profile, top-side-cooled packages, the devices can run cooler at higher power levels. CGD's monolithic ICeGaN® technology goes even further, integrating more functionality onto the device and therefore fewer external parts. It includes system monitoring through features like DESAT and temperature sensing to ensure reliability.  Together, these advantages deliver exactly what next-generation PSUs need: extreme power density and efficiency at 800V.

Learn what Physical AI is, understand how it differs from data centre AI, and why it is so relevant now. Explore the factors to consider when adding AI to your product, including tool and device selection. Leave with some pragmatic guidance for your next steps.